A MOSFET transistor that includes a trench gate structure offers important advantages over a planar transistor for high current, low voltage switching applications. A trench gate of a MOSFET device typically includes a trench extending from the source to the drain and having sidewalls and a floor that are each lined with a layer of thermally grown silicon dioxide. The lined trench is filled with doped polysilicon. The structure of the trench gate allows less constricted current flow and, consequently, provides lower values of specific on-resistance. Furthermore, the trench gate makes possible a decreased cell pitch in an MOSFET channel extending along the vertical sidewalls of the trench from the bottom of the source across the body of the transistor to the drain below. Channel density is thereby increased, which reduces the contribution of the channel to on-resistance.
A high density trench MOSFET device also includes a contact trench for making contact to source and body regions. Conventional processes for manufacturing of the high density trench MOSFET devices have used two independent masks for making gate trenches and contact trenches. FIG. 1A and FIG. 1B are cross-sectional views illustrating fabrication of a gate trench and contact trench of a vertical MOSFET structure of the prior art. As shown in FIG. 1A, a gate trench mask 102 is used to make a vertical gate trench 108. In a separate step, shown in FIG. 1B, a trench contact mask 104 is used to make a contact trench 110 on a same substrate 106 after the gate trench 108 has been formed. However, a mask overlay issue occurs when two masks 102 and 104 are used to form a vertical MOSFET structure because a well controlled spacing between the gate trench and nearby contact trench is required for high density MOSFET devices, which have increasingly smaller dimensions.
Schemes based on self-alignment processes have been proposed to solve this mask overlay issue. However, these proposed schemes, which use various constructs of alternating oxide and nitride blocking planar or sidewall spacers to create a contact trench that is self-aligned to the gate trench, are complicated to implement. In addition, the spacers may have uniformity problems, wherein spacers at the wafer center may be thicker or thinner than those at the wafer edge.
It is within this context that embodiments of the present invention arise. It would be desirable to develop a process which would use a single mask to pre-define both gate and contact trenches without using complicated multiple spacer approaches.